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1 of 26 optimum technology matching? applied gaas hbt ingap hbt gaas mesfet sige bicmos si bicmos sige hbt gaas phemt si cmos si bjt gan hemt functional block diagram rf micro devices?, rfmd?, optimum technology matching?, enabling wireless connectivity?, powerstar?, polaris? total radio? and ultimateblue? are trademarks of rfmd, llc. bluetooth is a trade- mark owned by bluetooth sig, inc., u.s.a. and licensed for use by rfmd. all other trade names, trademarks and registered tradem arks are the property of their respective owners. ?2006, rf micro devices, inc. product description 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . ordering information dig/flt vcc gpo1 lna vcc lna 2p lna 2n lna 3p lna 3n lna 4p lna 4n mix vcc lo vcc vco out vt vtc txb in lb vco vcc qb out q out ib out sclk clk in rx en gpo2 i out lna 1p lna 1n ssb sdi txb in hb tx en tx out lb tx out hb 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 lna3 lna4 dc correct quadrature generator lna1 lna2 polyphase filter quadrature mixer serial data interface rf2722 gsm/gprs/edge receiver the rf2722 is a highly-integrated receiver ic supporting gsm, gprs, and edge cellular standards in the gsm850, egsm, dcs, and pcs bands. the rf2722 sup- ports both very-low intermediate frequency (vlif) as well as direct conversion receive (dcr) architectures, reducing external component count and eliminating the need for if saw and rf interstage filters without compromising performance. the ic includes: four lna?s for multi-band support; an integrated voltage controlled oscillator (vco); automatic gain control (agc); a quadrature downconverting mixer; and, low and high band transmit buffers. chip functionality, including if agc set- ting, is controlled through a three-wire se rial data interface (sdi). the rf2722 is part of the polaris tm total radio tm solution. features ? gsm850, egsm, dcs & pcs operation ? supports both vlif & dcr modes ? integrated rf vco ? integrated lna?s support up to four rf bands ? edge receive compatible applications ? egsm/dcs handsets ? egsm/dcs/pcs handsets ? gsm850/pcs handsets ? gsm850/egsm/dcs/pcs handsets ? rf2722 gsm/gprs/edge receiver rf2722pcba-41x fully assembled evaluation board rev a4 ds050919 proposed part of the polaris tm total radio tm solution rohs compliant & pb-free product package style: qfn, 32-pin, 5x5
2 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . absolute maximum ratings parameter rating unit supply voltage -0.5 to +3.6 v storage temperature -40 to +150 c input voltage, any pin 3.6 v parameter specification unit condition min. typ. max. operating range temp=-30c to +85c, v cc =2.7v to 3.0v, all specifications referenced to 50 , unless spec- ified differently. temperature (t op ) -30 +85 c frequency range gsm850 rx 869 894 mhz low band gsm850 tx 824 849 mhz low band egsm rx 925 960 mhz low band egsm tx 880 915 mhz low band dcs rx 1805 1880 mhz high band dcs tx 1710 1785 mhz high band pcs rx 1930 1990 mhz high band pcs tx 1850 1910 mhz high band supply voltage (v cc ) 2.7 2.75 3.0 v pins 9 (mixvcc), 10 (lovcc), 16 (vcovcc), 24(dig/flt vcc), and 32 (lnavcc). power down current 10 arx en=0 active current rx vlif mode low band (850/950mhz) 64 77 91 ma all circuits on, (lna_curr=10, mix_curr=10) high band (1800/1900mhz) 63 76 90 ma all circuits on, (lna_curr=00, mix_curr=00) rx dcr mode low band (850/950mhz) 62.5 75.5 89.5 ma all circuits on, (lna_curr=10, mix_curr=10) high band (1800/1900mhz) 61.5 74.5 88.5 ma all circuits on, (lna_curr=00, mix_curr=00) tx mode low band (850/950mhz) 19.5 25 ma v cc =2.8v, p in =+4dbm high band (1800/1900mhz) 24.5 32 ma receiver system low side lo injection for all bands. except where noted, receiver specifications defined from lna input with i or q channel dif- ferential as output. cascaded noise figure low band (850/950mhz) 2.8 db +25c, lna_byp=0 high band (1850/1950mhz) 3.2 db +25c, lna_byp=0 caution! esd sensitive device. exceeding any one or a combination of the absolute maximum rating conditions may cause permanent damage to the device. extended application of absolute maximum rating conditions to the device may reduce device reliability. specified typical perfor- mance or functional operation of the devi ce under absolute maximum rating condi- tions is not implied. rohs status based on eudirective2002/95/ec (at time of this document revision). the information in this publication is believed to be accurate and reliable. however, no responsibility is assumed by rf micro devices, inc. ("rfmd") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. no license is granted by implication or otherwise under any patent or patent rights of rfmd. rfmd reserves the right to change component circuitry, recommended appli- cation circuitry and specifications at any time without prior notice.
3 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . low band (850/950mhz) 4.8 db -30-85c, lna_byp=0 high band (1850/1950mhz) 5.2 db -30-85c, lna_byp=0 noise figure with 3mhz blocker low band (850/950mhz) 3.8 4.8 db +25c; -26dbm at lna input. high band (1800/1900mhz) 4.7 5.7 db +25c; -29dbm at lna input. cascaded iip3 low band (850/950mhz) -12 dbm +25c; lna_byp=0; interferers at 0.8mhz and 1.6mhz high band (1850/1950mhz) -11 dbm low band (850/950mhz) -15 dbm -30-85c; lna_byp=0; interferers at 0.8mhz and 1.6mhz high band (1850/1950mhz) -14 dbm
4 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. receiver system, cont?d cascaded iip2 (vlif improvement not included) 1 tone (iip2 1 )/2 tone (iip2 1 ) lna_byp=0 low band (850/950mhz) 50 58 dbm 1 tone 44 52 dbm 2 tone high band (1850/1950mhz) 50 58 dbm 1 tone 44 52 dbm 2 tone cascaded p1db low band (850/950mhz) -22 -20 dbm minimum gain high band (1850/1950mhz) -23 -21 dbm minimum gain cascaded gain low band (850/950mhz) 54.5 57.5 60.5 db lna_byp=0; polyphase gain=0/12.6/7.4/1/8.4db high band (1850/1950mhz) 53.5 56.5 59.5 db lna_byp=0; polyphase gain=0/12.6/7.4/1/8.4db gain compression with 3mhz blocker low band (850/950mhz) 1.5 db +25c; lna_byp=0; -26dbm at lna input, with gain settings for a -99dbm wanted signal. high band (1850/1950mhz) 1.0 db +25c; lna_byp=0; -29dbm at lna input, with gain settings for a -99dbm wanted signal. lna gain step low band (850/950mhz) 15 16 17 db lna_byp=1 high band (1850/1950mhz) 17 18 19 db lna_byp=1 lo leakage low band (850/950mhz) -110 -100 dbm at the lna input. high band (1850/1950mhz) -110 -100 dbm at the lna input. 2lo suppression lna_byp=0 low band (850/950mhz) -22 -20 db high band (1850/1950mhz) -24 -22 db 3lo suppression lna_byp=0 low band (850/950mhz) -6 -4 db high band (1850/1950mhz) -16 -14 db 5lo suppression lna_byp=0 low band (850/950mhz) -22 -20 db high band (1850/1950mhz) -45 -43 db image balance low band (850/950mhz) 32 36 db high band (1850/1950mhz) 32 36 db lna input impedance low band (850/950mhz) 82-j156 high band (1850/1950mhz) 38-j66 lna input return loss low band (850/950mhz) -10 db with external match to 100 high band (1850/1950mhz) -10 db with external match to 100 absolute gain accuracy -3.2 +3.2 db for an y recommended agc setting across fre- quency and temperature in a single band, for power levels between -110dbm and -48dbm, assuming 1 gain calibration point per band.
5 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . relative gain accuracy -1 +1 db for any 20db gain step, using recommended agc gain settings for receive power levels in the range -110dbm and -48dbm.
6 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. vco +lo chain buffers, divide-by-2, di vide-by-4, divide-by-8 lo frequency 869 960 mhz vcohl=0 1805 1990 mhz vcohl=1 output level to synth -18.6 -17.4 -16.2 dbm 2k // 5pf load output frequency to synth 434.5 497.5 mhz vco_out=vco/8 tuning voltage 0.5 2.0 v tuning line input impedance 12 m dc measurement k vco * -27 -107 mhz/v lo phase noise, low band gsm850/egsm 0.6mhz -129.2 -127.2 dbc/hz 1.6mhz -138.4 -136.4 dbc/hz 3.0mhz -142.8 -140.8 dbc/hz 10.0mhz -145.0 -143.0 dbc/hz lo phase noise, high band dcs/pcs 0.6mhz -123.0 -121.0 dbc/hz 1.6mhz -133.1 -131.1 dbc/hz 3.0mhz -137.9 -135.9 dbc/hz 10.0 mhz -140.0 -138.0 dbc/hz * when used with an rf600x, the product of k vco xcharge pump current is calibrated to be within 5% of nominal value.
7 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. polyphase filter (4th order) vlif mode center frequency 99.5 107.0 114.5 khz half-bandwidth 180 200 220 khz in-band ripple 0.35 db 130khz half-bandwidth group delay 1.3 us 130khz half-bandwidth integrated attenuation 200khz 5.0 db 400khz 23.0 db 600khz 38.0 db >600khz 38.0 db i/q phase error 1.0 1.8 entire rx chain i/q amplitude error 0.1 0.25 db entire rx chain output capacitive load 20 pf output resistive load 30 k 30k rf6001/3 rx a/d input impedance. maximum output voltage swing 1 v p-p differential output common mode voltage 1.23 1.26 1.29 v static dc offset -160 +160 mv uncorrected direct conversion (dcr) mode center frequency -7.5 0 +7.5 khz half-bandwidth 180 200 220 khz in-band ripple 0.35 db 130khz half-bandwidth group delay 1.3 us 130khz half-bandwidth integrated attenuation 200khz 5.0 db 400khz 23.0 db 600khz 38.0 db >600khz 38.0 db i/q phase error 1.0 1.8 entire rx chain i/q amplitude error 0.1 0.25 db entire rx chain output capacitive load 20 pf output resistive load 30 k 30k rf6001/3 rx a/d input impedance. maximum output voltage swing 1 v p-p differential output common mode voltage 1.20 1.23 1.26 v dc offset (uncorrected) -160 +160 mv uncorrected
8 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. polyphase filter (4th order), cont?d polyphase input attenuator (dcr) (midband gain) gain -0.3 0 +0.3 db c_g1_1:0=11 -6.1 -5.5 -4.9 db c_g1_1:0=10 -14.0 -13.0 -12.0 db c_g1_1:0=00 first pole (dcr) (midband gain) gain 18.6 18.7 18.8 db f_g1_3:0=0111 17.5 17.6 17.7 db f_g1_3:0=0110 16.5 16.6 16.7 db f_g1_3:0=0101 15.5 15.6 15.7 db f_g1_3:0=0100 14.5 14.6 14.7 db f_g1_3:0=0011 13.5 13.6 13.7 db f_g1_3:0=0010 12.5 12.6 12.7 db f_g1_3:0=0001 11.5 11.6 11.7 db f_g1_3:0 = 0000 10.4 10.5 10.6 db f_g1_3:0 = 1111 9.4 9.5 9.6 db f_g1_3:0=1110 8.4 8.5 8.6 db f_g1_3:0=1101 7.4 7.5 7.6 db f_g1_3:0=1100 6.4 6.5 6.6 db f_g1_3:0=1011 5.4 5.5 5.6 db f_g1_3:0=1010 4.4 4.5 4.6 db f_g1_3:0=1001 3.4 3.5 3.6 db f_g1_3:0=1000 second pole (dcr) (midband gain) gain 7.3 7.4 7.6 db s_g2_0=1 -0.9 -0.7 -0.5 db s_g2_0=0 third pole (dcr) (midband gain) gain 0.9 1.0 1.1 db s_g2_1=1 -6.9 -6.8 -6.7 db s_g2_1=0 fourth pole (dcr) (midband gain) gain 13.9 14.3 14.7 db s_g3_1:0=11 8.1 8.4 8.7 db s_g3_1:0=01 2.2 2.5 2.8 db s_g3_1:0=00
9 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. dc offset correction residual dc error -20 +20 mv following dc offset correction. differential measurement. dc correction time 20 s dc offset drift referred to the lna input -126 dbm max gain measured in a window 150 s to 730 s after rxen is activated. clk in frequency 26 mhz clkf=0 tx buffer low band input power 3 6 dbm saturated output power 6.6 7.7 8.8 dbm p in =+4dbm output power variation -1.1 1.1 db dc current drain 5.2 7.2 9.3 ma dc with no rf input rf current drain 14 19.5 25 ma p in =+4dbm phase noise -167 dbc/hz 20mhz offset input vswr 3:1 p in =+4dbm output vswr 2:1 p in =+4dbm load vswr 3:1 p in =+4dbm reverse isolation 20 db txen=h forward isolation 20 db txen=l high band input power 3 6 dbm saturated output power 4.9 6.5 8.1 dbm p in =+4dbm output power variation -1.6 1.6 db dc current drain 8 11 13.8 ma dc with no rf input rf current drain 18 24.5 32 ma p in =+4dbm phase noise -160 dbc/hz input vswr 3:1 p in =+4dbm output vswr 2:1 p in =+4dbm load vswr 3:1 p in =+4dbm reverse isolation 35 db txen=h forward isolation 28 db txen=l
10 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . package drawing parameter specification unit condition min. typ. max. serial interface applies to pins sclk, sdi and ssb. input high voltage (v ih ) 0.7*v cc v input low voltage (v il ) 0.3*v cc v input high current (i ih )5 a input low current (i il )5 a setup time (t su )25 ns hold time (t h )10 ns rise/fall time (t rf )10ns clock to select time (t cs )10 ns clock pulse width high (t cwh )50 ns clock pulse width low (t cwl )50 ns digital output drivers apply to pins: gpo1, gpo2 output high voltage (v oh )v cc -0.05 v 1ma load v cc -0.50 v 10ma load output low voltage (v ol )0.05v1ma load 0.50 v 10ma load output rise/fall time (t rfo )5ns 26mhz reference clock input applies to clkin. frequency range (f r )26mhz input level (v inr )600 mv p-p ac-coupled mode input impedance (z inr )49k // 480ff interface voltage v cc /2 v internal bias transient startup time 250 ns input high voltage (v ih )0.7v cc v dc-coupled mode input low voltage (v il )0.3v cc v dc-coupled mode
11 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pin function description interface schematic 1lna 1p rf input to lna 1. internally matche d for 800mhz to 1000mhz operation. this pin possesses a dc voltage with respect to ground, and a series block- ing cap may be required in some applications. 2lna 1n complementary input to pin 1. this pin possesses a dc voltage with respect to ground, and a series blocking cap may be required in some applications. see pin 1. 3lna 2p rf input to lna 2. internally matched for 800 mhz to 1000 mhz operation. this pin possesses a dc voltage with respect to ground, and a series block- ing cap may be required in some applications. 4lna2n complementary input to pin 3. this pin possesses a dc voltage with respect to ground, and a series blocking cap may be required in some applications. see pin 3. 5lna 3p rf input to lna 3. internally matched for 1800 mhz to 2000 mhz opera- tion. this pin possesses a dc voltage with respect to ground, and a series blocking cap may be required in some applications. 6lna 3n complementary input to pin 5. this pin possesses a dc voltage with respect to ground, and a series blocking cap may be required in some applications. see pin 5. 7lna 4p rf input to lna 4. internally matched for 1800 mhz to 2000 mhz opera- tion. this pin possesses a dc voltage with respect to ground, and a series blocking cap may be required in some applications. 8lna 4n complementary input to pin 7. this pin possesses a dc voltage with respect to ground, and a series blocking cap may be required in some applications. see pin 7. 9mix vcc supply for the quadrature mixer. 10 lo vcc vco divider supply. 11 vco out output from the vco to drive the synthe sizer input. this is the vco divided by 8. 12 txb out lb low band tx buffer output. bias + - bias + - bias + - bias + - load mix vcc bias lo vcc vco out txb out lb
12 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pin function description interface schematic 13 txb out hb high band tx buffer output. 14 vt tuning control line for the vco. analog input. 15 vtc coarse vco tuning control driven by rf6001. digital input. 16 vco vcc supply for the rf vco. 17 txb in lb tx buffer low band input. this is a high impedance voltage-driven input designed to be driven by the rf6001/3 txvco output. 18 txb in hb tx buffer high band input. this is a high impedance voltage-driven input designed to be driven by the rf6001/3 txvco output. 19 tx en tx buffer enable. if the tx sel (crx1[2]) bit is set high, the tx buffers are enabled by this pin. if the tx sel bit is set low, this pin has no effect on the activation of the tx buffers. (see register map for more information.) the tx buffers are enabled by setting this pin high. the tx buffers are disabled by setting this pin low. 20 q out q-channel differential if output. 21 qb out complementary output to q out. 22 ib out complementary output to i out. 23 i out i-channel differential if output. 24 dig/flt vcc supply for all digital circuitry. supply for the filter. txb out hb vt vco vcc vco vcc vtc load vco vcc q out qb out ib out i out load dig/flt vcc
13 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pin function description interface schematic 25 ssb sdi enable input (active low). 26 sdi sdi data input. 27 sclk sdi clock input. 28 clk in clock input for the dc offset correction system. a 26mhz clock must be applied to this pin for proper operation of the dc offset correction system. 29 rx en set to vcc to activate the ic. set to gnd to deactivate. 30 gpo1 general purpose digital output 1. controlled via sdi programming. 31 gpo2 general purpose digital output 2. controlled via sdi programming. 32 rx vcc supply for the lna?s. ssb sdi sclk clk in rx en gpo1 gpo2 bias rx vcc
14 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . package drawing shaded lead is pin 1. -b- 2.50 typ. 2.37 typ. 5.00 sq. -a- 3 2 plcs 0.10 c a 2 plcs 0.10 c b 4.75 sq. 2 plcs 0.10 c a 2 plcs 0.10 c b 0.05 0.00 0.70 0.65 12 max -c- seating plane 0.90 0.85 0.05 c 0.50 3.45 3.15 sq. pin 1 id r.20 0.50 0.30 2 0.30 0.18 0.60 0.24 typ. c a b 0.10 m dimensions in mm.
15 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . detailed functional block diagram dig/flt vcc gpo1 lna vcc lna 2p lna 2n lna 3p lna 3n lna 4p lna 4n mix vcc lo vcc vco out vt vtc txb in lb vco vcc qb out q out ib out sclk clk in rx en gpo2 i out lna 1p lna 1n ssb sdi txb in hb tx en tx out lb tx out hb 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 lna3 lna4 dc correct quadrature generator lna1 lna2 polyphase filter quadrature mixer serial data interface
16 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . application schematic gpo2 26 mhz clock input rx enable from rf6001/3 or rx controller gpo1 150 egsm or gsm850 rf saw filter egsm/gsm850 rf input 100 pcs or dcs rf saw filter pcs/dcs rf input 100 dcs or pcs rf saw filter pcs/dcs rf input v cc v cc 4.7 f gnd vin ce bp vo vbatt 2.2 f national lp2985 2.8 v low-dropout regulator or equivalent 10 nf v cc hb txvco output from rf6001/3 tx en note if external pll is used for rf2722 vco control, vtc must be manually toggled to place the vco in appropriate frequency range to achieve lock. 150 egsm or gsm850 rf saw filter egsm/gsm850 rf input 4 5 3 1 2 to serial port controller v cc lb txvco output from rf6001/3 to rf31xx pa hb input to rf31xx pa lb input 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 lna3 lna4 dc correct quadrature generator lna1 lna2 polyphase filter quadrature mixer serial data interface to rf6001/3 or pll (see note) to rf6001/3 or vlif-to-baseband converter
17 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . application information functional description the rf2722 receiver ic will support gsm and edge cellular standards. four low noise amplifiers (lna?s) are provided to accommodate various combinations of up to four bands. the four lna?s share a common quadrature mixer. the active lna is selected and may be bypassed through the serial data interface (sdi). an rx local oscillator (vco) is provided. the vco is fully integr ated including an internal resonator and is band-selectable to cover the gsm850, egsm, dcs, and pcs bands. the desired signal is converted to either a vlif (100khz/120khz) or directly to dc, as determined by the setting of bit 1 in sd i register cf. once downconverted, the signal is filtered by an active rc po lyphase bandpass filter. the purpose of this filter is to provide some rejection to interfering signals such that the dyna mic range of the a/d converters will not be compromised. the rf2722 also includes two reverse isolation dual-band buffer amplifiers. these buffers are suitable for use in the transmit path between the vco output and the pa input to improve tr ansmit performance. the rf2722 accepts single-ended inputs from the rf6001/3 and provides single-ended outputs to the pa. dc correction operation the polaris rf2722 vlif/dcr ic will reduce the residual dc error of the i and q channels to less than 20mv within 20usec assuming that no input signal is present during the dc adapt ti me. the dc correction system will activate on the rising edge of rx_en if the sdi bit dc_en is programmed true. programming the sdi bit dc_st true can also activate the dc correction sys- tem. in this case the sdi bit dc_st will automatically return to a false state once the dc correction system is activated. the rf6001/3 also has an rx_en pin th at normally is set high at the same time as the rx_en of the rf2722. the dc correction system of the rf2722 will run for dc_time1 cycles of the clock present on clk_in divided by 16. this should be set for approximately 20usec. with a 26mhz clock on clk_in the setting of dc_time1 will be 20h. given the low levels of lo leakage to the lna inputs of the rf2722, the coarse dc adapt will be performed when rx_en rises with the lnas disabled. the residual dc error due to lo leakage when the lnas are enabled will be less than 5mv. once completed the dc correction outputs of the rf2722 will be held until power is removed from the ic or until another dc correction command is issued. during operation of the dc correction system the input signal should be muted so that the coarse dc correction system does not attempt to lock to the instantaneous signal level. this can be accomplished by disabling all lnas. this mode is selected if the lnd sdi bit is programmed true. this is performed for dc_time2 clock cycles of clk_in divided by 16 beginning at the dc correction command time so that the rf2722 will ha ve sufficient time to complete dc correction. if the radio employs a t/r switch then the t/ r switch can also be used to disable the signal instead of or in addition to dis- abling the lnas. the rf2722 can be used to automatically disabl e the t/r switch if the sdi bit trd is programmed true. in this case it is assumed that gpo1 and gpo2 provide on/off control for each of the possible bands of the receive side of the t/r switch. during the dc control time interval set by dc_time2 the outputs of gpo1 and gpo2 will be overridden by the sdi regis- ter trdc. the bits of this register can be set to 0 or 1 as need ed by the particular t/r switch implementation to deactivate th e receiver inputs. after dc_time2 has expired the normally programmed gpo states will return. after the coarse dc adapt time has elapsed then the rf6001/3 will require an additional time of approximately 50usec to complete the fine digital dc correction. note that the input signal may be present during the final dc correction time of the rf6001/3. for vlif modes this will not cause a dc problem since the rf6001/3 does an averaging of the dc error and there will be few components of the signal
18 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . near dc. in addition, the rf6001/3 will notch out 100khz converted dc components for channel bandwidths less than or equal to 85khz. the rf6003 will also notch out 120khz converted dc components for channel bandwidth of 90khz. this is only useful in vlif mode. in dcr mode there may be significant spectral content near dc during the final adapt of the rf6001/3. this may result in a significant dc component that will track the input desired signal level. it is assumed that the baseband dsp will be able to remove any such static dc error. in addition, if the dc adap t of the rf6001/3 is performed during the guard times then the spectral content of the input signal should be a tone in the region of 50khz to 70khz and should not interfere with the dc adapt process. if dc_time2 is extended to encompass the fine dc adapt time of the rf6001/3 then the input signal will not interfere with the adapt process as the lnas will be muted. however, if there is any residual lo leakage into the lna input then this error will remain after the dc correction process. this may be a sm aller residual error than that due to the input signals. a diagram depicting the composite dc correction and rx startup of the rf2 722 and rf6001/3 is presented below. gpo control the rf2722 allows the gpos to switch to an alternate setting defined by trdc during rx dc offset correction when trd is pro- grammed high. this is triggered by the rising edge of rx_en pi n and terminated by the expiration of dc_time2 in the rf2722. this mode of operation is used to turn off the lnas or redirect the t/r switch to tx mode during the dcoc time interval so that the signal present from the previous time slot or lo leakage will not cause an error in the dcoc. pll lockup initial calibration rx_en, en_se t=0usec rf6001/3 dcoc completed burst starts t=42 rf6001/3 filter data flushed receive valid data t=-20usec rf6001/3 pll lock completed t=-140usec activate rf2722/ rf6001/3 t=-90usec initial cal completed t=-120usec rf2722 dcocl completed system warm-up rf2722 turn on rf2722 rxi, q dcoc <20mv dc dc_time1 rf6001/3 rxi,q dcoc <80uv dc dc_time2 valid data 42 usec latency
19 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . in tx mode the rf2722 can also switch to an alternate set of gpo settings defined by trtxa at the rising edge of tx_en pin when trtx_en is programmed high. this functionality is used to re direct the t/r switch to rx mode during the synthesizer lock time so that the pa output due to feed-through from the vco will not violate the etsi time-mask specification. rx mode when rxen rises, dc_time2 starts in th e rf2722 and the part switches to the al ternate gpo settings defined in trdc. once the timer expires then the settings of the gpo's reve rt back to the originally programmed gpo sdi fields. tx mode when txen rises, the rf2722 gpos switch to the alternate gp o settings defined in trtxa. when txen falls, the rf2722 gpo settings revert back to the originally programmed gpo sdi fields. device control and programming the polaris rf2722 vlif/dcr ic provides a serial interface for programming the control settings. the interface consists of eight registers that are accessed individually via a six-bit addre ss word. (two registers are unused at this time and are inclu ded for future expansion.) the register map is shown below. each re gister plus the six address bits requires an 18-bit transfer (except register cf, which has 18 bits and so requires a 24-bit transfer). additional 'padding ' bits can be added between the address bits and the data bits, if longer transfer lengths ar e needed. since the rf2722 will be most likely used with the rf6001/3 then it is expected that six such padding bits will be used in each transfer to bring the total number of bits up to 2 4. this will then match the programming width of the rf6001/3. address register description 100000 crx1 agc, standby modes, lo phase cal 100001 crx2 dcoc and gpo 100010 crx3 dcoc 100011 crx4 dcoc 100100 crx5 lna, vco, mixer current settings, gain cal 100101 cf gain settings for the polyphase filters and lna?s. 100110 reserved reserved for future use. 100111 reserved reserved for future use. 011111 reset writing this address resets all sdi bits to their default states. rxen dc_time2 trdc gpo1,2 gpo trtxa gpo1,2 gpo tx_en gpo1,2
20 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . at power up the sdi address 011111 should be written to set up the default reset states of all registers. note that programmed settings will be lost if power to the part is removed. the figure below shows a timing diagram for the serial interface. the slave select (ss) pin is normally high. a serial transfer is initiated by taking ss low. the address and data bits on the seri al data in (sdi) pin are shifted in on rising edges of the ser ial clock (sclk) pin. twelve data bits follow the four address bits . the data is latched and changes take effect on the rising edge of ss. refer to the electrical specifications for the timing requirements. tcwh tcwl tcs th lsb ... msb ... tcs tsu ... tcs
21 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . receiver configuration register 1 (crx1) - address 100000 receiver configuration register 2 (crx2) - address 100001 location bit name default description crx1(11) reserved 0 reserved crx1(10:7) lo_ph_cal 0000 i/q phase calibration crx1(6) clk byp 1 if set to zero, then the clk_in pin is ac-coupled. if set to one, then the clk_in pin is dc-coupled. crx1(5) clkf 0 input clock frequency select. (must be set to 26mhz for normal operation.) programming this bit high activates a divide-by-two function on the clk_in pin. programming this bit low deactivates the divide-by-two function. the dc offset correction circuitry requires a 26mhz clock for proper operation. there- fore, clkf should be programmed low if a 26mhz clock is provided to the clk_in pin. 0=clk_in frequency is 26mhz 1=clk_in frequency is 52mhz crx1(4) vcosel 0 when set to zero, the vco is turned on and off by rx_en. when programmed high, the vco is controlled by the vcoen bit instead of rx_en. crx1(3) vcoen 0 when vcosel is set to one, then vcoen turns on and off the vco. when vcoen is set to zero, the vco is off. when vcoen is set to one, the vco is turned on. crx1(2) txsel 1 if programmed high, the tx buffers are enabled by the tx_en pin. if programmed low, the tx buffers are enabled by cf[16]. crx1(1:0) test 00 test output selection bits: the gpo1 pin provides test signal outputs as well as the activation signal for the rf6001 rx system. the available signals are shown below. 00 normal output of gpo1 pin 01 serial data shifting through configuration registers 10 msb bit of the vco calibration counter 11 dcadapt counter 2 output programming bits # of bits default description crx2(11) dc_st 0 if programmed high, the dc correction system is activated when the sdi word is loaded. dc_st will revert low once the dc correction system is activated. rx en needs to be high for dc_st to operate correctly. crx2(10) dc_en 1 if programmed high, the dc correction system is activated on the rising edge of rx_en (default=1). crx2(9) lnd 0 if programmed high, the lna?s are disabled during the time interval of the dc correc- tion system. crx2(8) trd 0 if programmed high, gpo1 and gpo2 follow trdc instead of the normal gp0 pro- gramming during the time interval defined by dc_time2. crx2(7) trtx_en 0 if programmed high, the functionality defined by trtxa is active. crx2(6) reserved 0 reserved crx2(5:4) trdc 00 if trd is set true, then during the time interval defined by dc_time2, gpo1 and gpo2 are reassigned as follows. gpo1=trdc[0] gpo2=trdc[1] crx2(3:2) trtxa 00 if trtx_en is programmed high, while txen pin is high the gpo outputs are reassigned as follows: gpo1=trtxa[0] gpo2=trtxa[1] crx2(1:0) gpo 00 the states of each bit within this word are transferred to the corresponding gp0 pin as follows. gpo1=gpo[0] gpo2=gpo[1]
22 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . receiver configuration register 3 (crx3) - address 100010 receiver configuration register 4 (crx4) - address 100011 receiver configuration register 5 (crx5) - address 100100 polyphase filter gain register (cf) - address 100101 programming bits # of bits defaults description crx3(11:10) reserved 00 reserved crx3(9:2) dc_time1 20h sets the number of 26mhz/16 clock cycles from activation until the rf2722 dcoc system is frozen. crx3(1:0) reserved 00 reserved programming bits # of bits defaults description crx4(11:10) reserved 00 reserved crx4(9:0) dc_time2 124h sets the number of 26mhz/16 clock cycles from activation until the lna?s and/or the rx t/r switch are reactivated. programming bits # of bits defaults description crx5(11:9) gain_cal 011 i/q gain calibration crx5(8:6) reserved 000 reserved crx5(5:4) reserved 00 reserved crx5(3:2) lna_curr 10 these bits control the lna current as shown below. low band high band 00 11ma 13.2ma 01 12.8ma 15ma 10 14.6ma 16.9ma 11 16.4ma 18.7ma crx5(1:0) mix_curr 10 these bits control the mixer current as shown below. 00 12.5ma 01 13.5ma 10 14.4ma 11 15.6ma programming bits # of bits defaults description cf(17) tx_hl 0 if programmed low, enables cellular /gsm tx buffer. if programmed high, enables pcs/dcs tx buffer. cf(16) tx_en 0 if tx_sel is set false, tx buffers are controlled by this bit. cf(15:13) lna_sel 101 selects the active lna. 000 lna1 (us/gsm) 001 lna2 (us/gsm) 010 lna3 (dcs/pcs) 011 lna4 (dcs/pcs) 100 all lna?s off 101 all lna?s off cf(12) vcohl 0 if programmed low, divides the vco by 2 and routes signal through us cellular/gsm filter path. if programmed high, the vco signal is routed through pcs/dcs filter path. cf(11:8) f_g1 0000 selects the fine gain setting of the first pole of the filter. the gain in db at the mid- band (0hz for dcr) is as shown below. 0000=11.6db0001=12.6db0010=13.6db0011=14.6db 0100=15.6db0101=16.6db0110=17.6db0111=18.7db 1000=3.5db1001=4.5db1010=5.5db1011=6.5db 1100=7.5db1101=8.5db1110=9.5db1111=10.5db cf(7:6) c_g1 11 selects the coarse input attenuation setting of the first pole of the filter. 00=-13db01=n/a10=-5.5db11=0db
23 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . cf(5) s_g2_0 1 selects the gain setting at midband of the second filter stage. 0=-0.7db1=+7.4db cf(4) s_g2_1 1 selects the gain setting at midband of the third filter stage. 0=-6.8db1=+1db cf(3:2) s_g3 00 selects the gain setting at midband of the output buffer. 00=2.5db01=8.4db10=n/a11=14.3db cf(1) vds 0 selects vlif mode if programmed low. selects dcr mode if programmed high. cf(0) lna_byp 0 if set to zero, the lna is active. if set to one, the lna is bypassed with a front end gain reduction of: 11.9db in low band; 10.4db in high band.
24 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pcb design requirements pcb surface finish the pcb surface finish used for rfmd's qualification process is electroless nickel, immersio n gold. typical thickness is 3 inch to 8 inch gold over 180 inch nickel. pcb land pattern recommendation pcb land patterns are based on ipc-sm-782 standards when po ssible. the pad pattern shown has been developed and tested for optimized assembly at rfmd; however, it may require so me modifications to address co mpany specific assembly pro- cesses. the pcb land pattern has been develope d to accommodate lead and package tolerances. pcb metal land pattern a a a a a a a a b b b b b b b b c a a a a a a a a b b b b b b b b 3.50 typ. 0.50 typ. 0.50 typ. 0.55 typ. 0.55 typ. 1.75 typ. 1.75 typ. 3.50 typ. a = 0.64 x 0.28 (mm) typ. b = 0.28 x 0.64 (mm) typ. c = 3.50 (mm) sq. pin 1 pin 32 pin 24 pin 16 dimensions in mm. figure 1. pcb metal land pattern (top view)
25 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pcb solder mask pattern liquid photo-imageable (lpi) so lder mask is recommended. the solder mask fo otprint will match what is shown for the pcb metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. the center-grounding pad shall also have a solder mask clearance. expansion of the pads to create solder mask clearance can be provided in the master data or reques ted from the pcb fabrication supplier. a a a a a a a a b b b b b b b b a a a a a a a a b b b b b b b b c 3.50 typ. 0.50 typ. 0.50 typ. 0.55 typ. 1.75 typ. 1.75 typ. 0.55 typ. 3.50 typ. a = 0.74 x 0.38 (mm) typ. b = 0.38 x 0.74 (mm) typ. c = 3.60 (mm) sq. pin 1 pin 32 pin 24 pin 16 dimensions in mm. figure 2. pcb solder mask (top view)
26 of 26 rf2722 proposed rev a4 ds050919 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . thermal pad and via design the pcb land pattern has been designed with a thermal pad th at matches the exposed die paddle size on the bottom of the device. thermal vias are required in the pcb layout to effectively conduct heat away from the package. the via pattern shown has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. the via pattern used for the rfmd qualification is based on th ru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm pl ating on via walls. if micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. via 0.203 - 0.330 (mm) finished hole 0.5 - 1.2 (mm) grid figure 3. thermal pad and via design (rfmd qualification)

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